Dynamic Voltage And Frequency Scaling Research Articles

Energy-efficient scheduling for parallel applications with reliability and time constraints on heterogeneous distributed systems

Reliability is a crucial index of the system, and many safety-critical applications have reliability requirements and deadline constraints. In addition, in order to protect the environment and reduce system operating costs, it is necessary to minimize energy consumption as much as possible. This paper considers parallel applications on heterogeneous distributed systems and proposes two algorithms to minimize energy consumption for meeting the deadline and satisfying the reliability requirement of the applications. The first algorithm is called minimizing scheduling length while satisfying the reliability requirement (MSLSRR). It first transforms the reliability requirement of the application into the reliability requirement of the task and then assigns the task to the processor with the earliest finish time. Since the reliability generated by MSLSRR is often higher than the reliability requirement of the application, and the scheduling length is also less than the deadline, an algorithm called improving energy efficiency (IEE) is designed, which redefined the minimum reliability requirement for the task and applied dynamic voltage and frequency scaling (DVFS) technique for energy conservation. The proposed algorithms are compared with existing algorithms by using real parallel applications. Experimental results demonstrate that the proposed algorithms consume the least energy.

Online Energy-Aware Scheduling for Deadline-Constrained Applications in Distributed Heterogeneous Systems

In the current computing environment, the significance of distributed heterogeneous systems has gained prominence. The research on scheduling problems in distributed systems that consider energy consumption has garnered substantial attention due to its potential to enhance system stability, achieve energy savings, and contribute to environmental preservation. However, efficient scheduling in such systems necessitates not only the consideration of energy consumption but also the ability to adapt to the dynamic nature of the system. To tackle these challenges, we propose an online energy-aware scheduling algorithm for deadline-constrained applications in distributed heterogeneous systems, leveraging dynamic voltage and frequency scaling (DVFS) techniques. First, the algorithm models the continuously arriving applications and heterogeneous processors and proposes a novel task-sorting method to prioritize tasks, ensuring that more applications are completed within their respective deadlines. Second, the algorithm controls the selection range of processors based on the task’s subdeadline and assigns the task to the processor with the minimum energy consumption. Through experiments conducted with randomly generated applications, our approach consistently exhibits superior performance when compared to similar scheduling algorithms.

LEC-MiCs: Low-Energy Checkpointing in Mixed-Criticality Multi-Core Systems

With the advent of multicore platforms in designing Mixed-Criticality Systems (MCSs), simultaneous management of reliability and energy while guaranteeing an acceptable service level for low-criticality tasks is a crucial challenge. To ensure the reliability of the MCSs against transient faults, fault-tolerant techniques are employed which will increase energy consumption. To mitigate the energy overhead, the Dynamic Voltage and Frequency Scaling (DVFS) technique will be exploited. However, this technique might lead to violating the timing constraints of high-criticality tasks. Therefore, this paper presents, for the first time, the low-energy checkpointing technique to guarantee the reliability of multiple preemptive periodic mixed-criticality tasks in a multicore platform. In contrast to the previous works in checkpointing technique which consider a specific number of faults that all the tasks in the system should tolerate, in this paper, the number of tolerable faults for each execution section of a task, and in each voltage and frequency level is determined through proposed formulas to meet the reliability target based on safety standards. Then, our proposed method determines the number of checkpoints and their non-uniform intervals for the normal and overrun sections of each task to reduce energy consumption, respectively. Moreover, the unified demand bound function (DBF) analysis is proposed for analyzing the schedulability of the task set, where each high-criticality task meets its timing and reliability constraints, and low-criticality tasks execute based on their derived guaranteed periods in each operational mode of the system. Experimental results show that our proposed scheme meets the timing and reliability constraints while at the same time, improving the QoS of low-criticality tasks, and managing energy consumption with an average of 29.49%, and 32.78%, respectively.

Architectural and Technological Approaches for Efficient Energy Management in Multicore Processors

Benchmarks play an essential role in the performance evaluation of novel research concepts. Their effectiveness diminishes if they fail to exploit the available hardware of the evaluated microprocessor or, more broadly, if they are not consistent in comparing various systems. An empirical analysis of the consecrated Splash-2 benchmarks suite vs. the latest version Splash-4 was performed. It was shown that on a 64-core configuration, half of the simulated benchmarks reach temperatures well beyond the critical threshold of 105 °C, emphasizing the necessity of a multi-objective evaluation from at least the following perspectives: energy consumption, performance, chip temperature, and integration area. During the analysis, it was observed that the cores spend a large amount of time in the idle state, around 45% on average in some configurations. This can be exploited by implementing a predictive dynamic voltage and frequency scaling (DVFS) technique called the Simple Core State Predictor (SCSP) to enhance the Intel Nehalem architecture and to simulate it using Sniper. The aim was to decrease the overall energy consumption by reducing power consumption at core level while maintaining the same performance. More than that, the SCSP technique, which operates with core-level abstract information, was applied in parallel with a Value Predictor (VP) or a Dynamic Instruction Reuse (DIR) technique, which rely on instruction-level information. Using the SCSP alone, a 9.95% reduction in power consumption and an energy reduction of 10.54% were achieved, maintaining the performance. By combining the SCSP with the VP technique, a performance increase of 8.87% was obtained while reducing power and energy consumption by 3.13% and 8.48%, respectively.

Dynamic Voltage and Frequency Scaling as a Method for Reducing Energy Consumption in Ultra-Low-Power Embedded Systems

Dynamic voltage and frequency scaling (DVFS) is a technique used to optimize energy consumption in ultra-low-power embedded systems. To ensure sufficient computational capacity, the system must scale up its performance settings. The objective is to conserve energy in times of reduced computational demand and/or when battery power is used. Fast Fourier Transform (FFT), Cyclic Redundancy Check 32 (CRC32), Secure Hash Algorithm 256 (SHA256), and Message-Digest Algorithm 5 (MD5) are focused functions that demand computational power to achieve energy-efficient performance. Selected operations are analyzed from the energy consumption perspective. In this manner, the energy required to perform a specific function is observed, thereby mitigating the influence of the instruction set or system architecture. For stable operating voltage scaling, an exponential model for voltage calculation is presented. Statistical significance tests are conducted to validate and support the findings. Results show that the proposed optimization technique reduces energy consumption for ultra-low-power applications from 27.74% to up to 47.74%.

Artificial Intelligence Driven Power Optimization in IOT-Enabled Wireless Sensor Networks

The widespread use of Wireless Sensor Networks (WSN) in Internet of Things (IoT) causes energy efficiency issues. This paper proposes an AI-based solution to this problem. The propose an AI-Driven Power Optimization framework for IoT-enabled WSN using Deep Q-Network (DQN) and Dynamic Voltage and Frequency Scaling (DVFS). These techniques can adapt to changing network conditions and reduce power consumption when used together. Sensor nodes provide environmental parameters, battery status, and network behavior data to the AI-driven framework DQN is implemented after data preprocessing to learn and make power management decisions using reinforcement learning.   Neural network-driven agent operates in a state and action space. It optimizes energy use with rewards. Real-time hardware power adjustment is done using DVFS. DVFS precise control and AI-driven decision-making create a comprehensive power optimization strategy. AI adapts to new challenges and optimizes network lifespan by improving its power management policies. Experimental implementations of the proposed framework show significant energy savings, network lifespan extension, and QoS improvements. AI-Driven Power Optimization in IoT-enabled WSN is proven effective and flexible. This study shows the potential of AI, specifically DQN and DVFS, in IoT-enabled WSN. This AI-Driven Power Optimization framework addresses energy efficiency and improves IoT sensor networks. AI improves power optimization in IoT-enabled WSN making IoT deployments more sustainable and resilient.

Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF

This article tackles the problem of optimal placement of complex real-time embedded applications on heterogeneous platforms. Applications are composed of directed acyclic graphs of tasks, with each directed-acyclic-graph (DAG) having a minimum inter-arrival period for its activation requests and an end-to-end deadline within which all of the computations need to terminate since each activation. The platforms of interest are heterogeneous power-aware multi-core platforms with Dynamic Voltage and Frequency Scaling (DVFS) capabilities, including big.LITTLE Arm architectures and platforms with GPU or FPGA hardware accelerators with Dynamic Partial Reconfiguration capabilities. Tasks can be deployed on CPUs using partitioned EDF-based scheduling. Additionally, some of the tasks may have an alternate implementation available for one of the accelerators on the target platform, which are assumed to serve requests in non-preemptive FIFO order. The system can be optimized by minimizing power consumption, respecting precise timing constraints, maximizing the applications’ slack, respecting given power consumption constraints, or even a combination of these, in a multi-objective formulation. We propose an off-line optimization of the mentioned problem based on mixed-integer quadratic constraint programming (MIQCP). The optimization provides the DVFS configuration of all the CPUs (or accelerators) capable of frequency switching and the placement to be followed by each task in the DAGs, including the software-vs.-hardware implementation choice for tasks that can be hardware accelerated. For relatively big problems, we developed heuristic solvers capable of providing suboptimal solutions in a significantly reduced time compared to the MIQCP strategy, thus widening the applicability of the proposed framework. We validate the approach by running a set of randomly generated DAGs on Linux under SCHED_DEADLINE, deployed onto two real boards, one with Arm big.LITTLE architecture, the other with FPGA acceleration, verifying that the experimental runs meet the theoretical expectations in terms of timing and power optimization goals.

A 33nW Fully Autonomous SoC With Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for mm-Scale System-in-Fiber.

This article presents a fully autonomous system-on-chip (SoC) that can be distributed along a fiber strand, capable of simultaneously harvesting energy, cooperatively scaling performance, sharing power, and booting-up with other in-fiber SoCs for ultra-low-power (ULP) sensing applications. Utilizing a custom switched capacitor energy harvesting and power management unit (EHPMU), the SoC can efficiently redistribute and reuse harvested energy along the fiber. Integrated on-chip, the ULP RISC-V digital core and temperature sensor enable energy-efficient sensing and computation at nanowatt power levels. A dedicated ripple boot-up and cooperative dynamic voltage and frequency scaling (DVFS) further optimize the operation and physical size of the system. Fabricated in 65 nm, measurement results show that the proposed SoC achieves 33 nW power consumption for the whole chip under 92 Lux lighting condition and can reduce control power down to 2.7 nW for the EHPMU. With the proposed power sharing and cooperative DVFS techniques, the SoC reduces the illuminance needed to stay alive by >7× down to 12 Lux. Integrated into a mm-scale polymer fiber, our SoC demonstrates the feasibility of fully autonomous and ULP on-body sensing systems in resource-constrained fiber environments.

Deploying an energy efficient, secure & high-speed sidechain-based TinyML model for soil quality monitoring and management in agriculture

This paper presents an innovative deployment strategy for a power-aware and delay-aware TinyML model optimized for agricultural soil quality monitoring and management. The proposed method employs an enhanced fusion of Dynamic Voltage and Frequency Scaling (DVFS), Sleep/Wake Strategies based on Genetic Algorithms, Energy Harvesting, and Task Partitioning. Through this method, the model reduces energy consumption by 8.5% and delay by 10.4%, while maintaining accuracy comparable to state-of-the-art techniques such as Convolutional Neural Networks (CNNs), Recurrent Neural Networks (RNNs), and Q Learning techniques. The proposed model also uses a Proof-of-Energy Efficiency (PoEE) based consensus for creation of new blocks. These blocks are added to different sidechains for strengthening the security levels. While blockchains require higher energy during mining, the proposed PoEE Model uses a light weight consensus, which is backed by Q Learning based sidechain formation process. This lightweighted combination allows the model to reduce delay, maintain lower energy consumption, with better communication throughput even under multiple attack scenarios. This model is necessary due to the growing demand for sustainable and accurate agricultural practices. The quality of the soil is crucial to soil yield and productivity. Monitoring and managing soil conditions enables farmers to optimize irrigation, fertilization, and overall resource allocation, leading to an increase in soil yield and a decrease in environmental impacts. However, the deployment of energy-efficient and low-latency TinyML models is essential to enable real-time decision-making in agricultural settings with limited resources. This power-aware and delay-aware TinyML model has applications in various agricultural real-time scenarios. It can be used to continuously monitor soil quality parameters including moisture content, pH level, and nutrient levels for various farm types. Incorporating sensors and low-power microcontrollers, the model enables on-site analysis and timely farmer feedbacks. The decreased energy consumption extends the battery life of deployed devices, whereas the decreased delay ensures that soil management interventions and treatments are responsive and timely for different scenarios.

Lightning: Leveraging DVFS-induced Transient Fault Injection to Attack Deep Learning Accelerator of GPUs

Graphics Processing Units (GPU) are widely used as deep learning accelerators because of its high performance and low power consumption. Additionally, it remains secure against hardware-induced transient fault injection attacks, a classic type of attacks that have been developed on other computing platforms. In this work, we demonstrate that well-trained machine learning models are robust against hardware fault injection attacks when the faults are generated randomly. However, we discover that these models have components, which we refer to as sensitive targets, that are vulnerable to faults. By exploiting this vulnerability, we propose the Lightning attack, which precisely strikes the model’s sensitive targets with hardware-induced transient faults based on the Dynamic Voltage and Frequency Scaling (DVFS). We design a sensitive targets search algorithm to find the most critical processing units of Deep Neural Network (DNN) models determining the inference results, and develop a genetic algorithm to automatically optimize the attack parameters for DVFS to induce faults. Experiments on three commodity Nvidia GPUs for four widely-used DNN models show that the proposed Lightning attack can reduce the inference accuracy by 69.1% on average for non-targeted attacks, and, more interestingly, achieve a success rate of 67.9% for targeted attacks.

NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores

Thermal optimization of a heterogeneous clustered multi-core processor under user-defined QoS targets requires application migration and DVFS. However, selecting the core to execute each application and the VF levels of each cluster is a complex problem because (1) the diverse characteristics and QoS targets of applications require different optimizations, and (2) per-cluster DVFS requires a global optimization considering all running applications. State-of-the-art resource management for power or temperature minimization either relies on measurements that are commonly not available (such as power) or fails to consider all the dimensions of the optimization (e.g., by using simplified analytical models). To solve this, ML methods can be employed. In particular, IL leverages the optimality of an oracle policy, yet at low run-time overhead, by training a model from oracle demonstrations. We are the first to employ IL for temperature minimization under QoS targets. We tackle the complexity by training NN at design time and accelerate the run-time NN inference using NPU. While such NN accelerators are becoming increasingly widespread, they are so far only used to accelerate user applications. In contrast, we use for the first time an existing accelerator on a real platform to accelerate NN-based resource management. To show the superiority of IL compared to RL in our targeted problem, we also develop multi-agent RL-based management. Our evaluation on a HiKey 970 board with an Arm big.LITTLE CPU and NPU shows that IL achieves significant temperature reductions at a negligible run-time overhead. We compare TOP-IL against several techniques. Compared to ondemand Linux governor, TOP-IL reduces the average temperature by up to 17 ˆC at minimal QoS violations for both techniques. Compared to the RL policy, our TOP-IL achieves 63 % to 89 % fewer QoS violations while resulting similar average temperatures. Moreover, TOP-IL outperforms the RL policy in terms of stability. We additionally show that our IL-based technique also generalizes to different software (unseen applications) and even hardware (different cooling) than used for training.

Power-Efficient and Aging-Aware Primary/Backup Technique for Heterogeneous Embedded Systems

One of the essential requirements of embedded systems is a guaranteed level of reliability. In this regard, fault-tolerance techniques are broadly applied to these systems to enhance reliability. However, fault-tolerance techniques may increase power consumption due to their inherent redundancy. For this purpose, power management techniques are applied, along with fault-tolerance techniques, which generally prolong the system lifespan by decreasing the temperature and leading to an aging rate reduction. Yet, some power management techniques, such as Dynamic Voltage and Frequency Scaling (DVFS), increase the transient fault rate and timing error. For this reason, heterogeneous multicore platforms have received much attention due to their ability to make a trade-off between power consumption and performance. Still, it is more complicated to map and schedule tasks in a heterogeneous multicore system. In this paper, for the first time, we propose a power management method for a heterogeneous multicore system that reduces power consumption and tolerates both transient and permanent faults through primary/backup technique while considering core-level power constraint, real-time constraint, and aging effect. Experimental evaluations demonstrate the efficiency of our proposed method in terms of reducing power consumption compared to the state-of-the-art schemes, together with guaranteeing reliability and considering the aging effect.

Energy management of fault-tolerant real-time embedded systems through switching-activity-based techniques

Energy management and fault tolerance are essential aspects in designing most real-time embedded systems, and dynamic voltage and frequency scaling (DVFS) is a fundamental approach in energy management. Using DVFS can lead to a considerable decrease in the system's reliability as the rate of transient faults increases due to low voltage and frequency. This study focuses on finding and implementing methods that address the following three issues in hard real-time embedded systems: energy consumption, fault tolerance, and time limitations. Switching activity depends on the nature of tasks. Since the switching activity is task-specific, the energy consumption of a task can be significantly greater than that of other tasks. As far as we know, previous studies on the power management of fault-tolerant real-time systems have not considered switching activity, so the impact of this factor is considered in this study. Multiple heuristic methods are proposed based on the switching activity factor to minimize energy consumption while sustaining the system's original reliability. In the proposed methods, the order of task execution is determined based on task switching activities. The methods are developed for both periodic and frame-based task models. The results show that the proposed methods can decrease the energy consumption by 12.7 %∼35.5 % for the periodic task model and 17.4 %∼45.2 % for the frame-based task model while preserving the system's reliability.

Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power Regulation

3D-stacked processor-memory systems stack memory (DRAM banks) directly on top of logic (CPU cores) using chiplet-on-chiplet packaging technology to provide the next-level computing performance in embedded platforms. Stacking, however, severely increases the system’s power density without any accompanying increase in the heat dissipation capacity. Consequently, 3D-stacked processor-memory systems suffer more severe thermal issues than their non-stacked counterparts. Nevertheless, 3D-stacked processor-memory systems do inherit power (thermal) management knobs from their non-stacked predecessors - namely Dynamic Voltage and Frequency Scaling (DVFS) for cores and Low Power Mode (LPM) for memory banks. In the context of 3D-stacked processor-memory systems, DVFS and LPM are performance- and power-wise deeply intertwined. Their non-unified independent use on 3D-stacked processor-memory systems results in sub-optimal thermal management. The unified use of DVFS and LPM for thermal management for 3D-stacked processor-memory systems remains unexplored. The lack of implementation of LPM in thermal simulators for 3D-stacked processor-memory systems hinders real-world representative evaluation for a unified approach. We extend the state-of-the-art interval thermal simulator for 3D-stacked processor-memory systems CoMeT with an LPM power management knob for memory banks. We also propose a learning-based thermal management technique for 3D-stacked processor-memory systems that employ DVFS and LPM in a unified manner. Detailed interval thermal simulations with the extended CoMeT framework show a 10.15% average response time improvement with the PARSEC and SPLASH-2 benchmark suites, along with widely-used Deep Neural Network (DNN) workloads against a state-of-the-art thermal management technique for 2.5D processor-memory systems (ported directly to 3D-stacked processor-memory systems) that also proposes unified use of DVFS and LPM.

Designing A Multi-Frequency Low Power Low-Density Parity Check (LDPC) Encoder with A Dynamic Voltage and Frequency Scaling (DVFS) Approach

Designing A Multi-Frequency Low Power Low-Density Parity Check (LDPC) Encoder with A Dynamic Voltage and Frequency Scaling (DVFS) Approach

Time–Energy Correlation for Multithreaded Matrix Factorizations

The relationship between time and energy is an important aspect related to energy savings in modern multicore architectures. In this paper, we investigated and analyzed the correlation between time and energy. We compared the execution time and energy consumption of the LU factorization algorithms (versions with and without pivoting) and Cholesky with the Math Kernel Library (MKL) on a multicore machine. To reduce the energy of these multithreaded factorizations, the Dynamic Voltage and Frequency Scaling (DVFS) technique was used. This technique allows the clock frequency to be scaled without changing the implementation. In particular, we studied the correlations between time and energy using two metrics: Energy Delay Product (EDP) and Greenup, Powerup, and Speedup (GPS-UP). An experimental evaluation was performed on an Intel Xeon Gold multicore machine as a function of the number of threads and the clock speed. Our test results showed that scalability in terms of execution time, expressed by the Speedup metric, had values close to a linear function as the number of threads increased. In contrast, the scalability in terms of energy consumption, expressed by the Greenup metric, had values close to a logarithmic function as the number of threads increased. The use of the EDP and GPS-UP metrics allowed us to evaluate the impact of the optimized code (DVFS and increase in the number of threads) on the time and energy consumption and to determine a better green category representing energy savings without losing performance.

Vincent: Green hot methods in the JVM

In this paper, we show the energy efficiency of Java applications can be improved by applying Dynamic Voltage and Frequency Scaling (DVFS) inside the Java Virtual Machine (JVM). We augment the JVM to record the energy consumption of hot methods as the underlying CPU is run at different clock frequencies; after all the frequency possibilities for a method have been explored, the execution of the method in an optimized run is set to the CPU frequency that leads to the most energy-efficient execution for that method. We introduce a new sampling methodology to overcome the dual challenges in our design: both the underlying measurement mechanism for energy profiling and the DVFS for energy optimization are overhead-prone. We extend JikesRVM with our approach and benchmark it over the DaCapo suite on a server-class Linux machine. Experiments show we are able to use 14.9% less energy than built-in power management in Linux, and improve energy efficiency by 21.1% w.r.t. the metric of Energy-Delay Product (EDP).

Fine-Grained Online Energy Management of Edge Data Centers Using Per-Core Power Gating and Dynamic Voltage and Frequency Scaling

It is important to minimize the energy consumption of large-scale, geographically distributed edge data centers (EDCs). While modern processing units (PUs) have energy-saving features like Dynamic Voltage and Frequency Scaling (DVFS) and Per-Core Power Gating (PCPG), optimization is still complex and requires a holistic approach. This paper presents a new decentralized, three-timescale, online optimization approach that enables multicore micro data centers (MDCs) to optimize their per-PU power states, per-enabled-PU voltage-frequency levels and offloading schedules at three different timescales. The key idea is that we employ multi-timescale Lyapunov optimization to decouple the energy minimization between workload scheduling and result delivery at a small timescale and PU configuration at large timescales. Another important aspect is that we apply the primal decomposition to decouple the PU configuration between a per-enabled-PU voltage-frequency level at an intermediate timescale and a per-PU power state at a large timescale. Experiments demonstrate that the proposed approach improves energy efficiency significantly by up to 4.5 times in our considered lightly loaded situations where DVFS alone does not work effectively, compared to existing benchmarks.

Towards Improved Power Management in Cloud GPUs

As modern server GPUs are increasingly power intensive, better power management mechanisms can significantly reduce the power consumption, capital costs, and carbon emissions in large cloud datacenters. This paper uses diverse datacenter workloads to study the power management capabilities of modern GPUs. We find that current GPU management mechanisms have limited compatibility and monitoring support under cloud virtualization. They have sub-optimal, imprecise, and non-intuitive implementations of Dynamic Voltage and Frequency Scaling (DVFS) and power capping. Consequently, efficient GPU power management is not widely deployed in clouds today. To address these limitations, we make actionable recommendations for GPU vendors and researchers.

Energy-aware fully-adaptive resource provisioning in collaborative CPU-FPGA cloud environments

Cloud warehouses have been exploiting multi-tenancy in CPU-FPGA collaborative environments, so clients can share the same infrastructure, achieving scalability and maximizing resource utilization. Therefore, the distribution of tasks across CPU and FPGA must be well-balanced so performance and energy are optimized in a highly variant workload scenario. In this paper, we take a step further and, in contrast to existing approaches, exploit DVFS (Dynamic Voltage and Frequency Scaling) on the CPU, together with an intelligent CPU-FPGA resource provisioning mechanism, to further improve energy. For that, we propose EASER, an end user-transparent framework that employs multiple strategies and dynamically selects the most appropriate one to optimize resource provisioning and DVFS according to the warehouse needs, workload properties, and target architecture. Our synergistic DVFS optimization brings up to 22% additional energy gains over our dynamic provisioning alone. Compared to fixed single strategies with DVFS, EASER brings, on average, 71% of energy gains.